for further information contact your local stmicroelectronics sales office. june 2013 docid024749 rev 1 1/4 stih206 advanced hd avc processor with integrated low power standby controller for entry market data brief features ? st40 applications cpu with 256 kbyte l2 cache ? 16-bit lmi supporting ddr3 up to 667 mhz ? decoding of h.264, mpeg2, vc-1 and avs hd video streams ? 3dtv decoding and display compatible with hdmi 1.4b ? extensive connectivity (two usb 2.0 ports; ethernet mii/rmii/tmii port; sd/mmc card port; esata port; pcie) ? secure booting from slc nand flash or serial nor flash ? low-power process and architecture ? integrated low power standby controller ? high-quality video resizing and de-interlacing ? integrated ethernet phy ? targets two layer pcb designs for low-end zapper stb applications ? package: pbga 27 27 x 2.19 description the stih206 uses the latest process technology to provide a cost-effective, feature rich, highly integrated soc for set-top boxes (stbs). it is targeted at the advanced decoding stb market across all networks (cable/ satellite/dtt/x-dsl/ip) worldwide, and is suitable both for operator markets (with advanced security) and retail markets. the stih206 provides a solution for operators and manufacturers to specify a range of cost-effective, high-performance stbs including basic zappers, interactive stbs, ip clients, and dvr stbs with content delivery possible using broadcast or broadband networks or both (hybrid stbs). jtag stb peripherals i/o resets analog out clocks modes pcm i/o s/pdif out external interrupts clock gen system serv peripherals ssc uart rtc pwm gpios ir/uhf connectivity transport security st231 cpu blitter tile sram video planes graphic planes aux vdp dei, iqi dual denc tel e t e xt dacs hdmi 1.4 audio i/o display video i/o audio decoder st231 cpu video decoder emi spi system interfaces main vdp cpu/fpu mmu interrupts i cache d cache timer st40-300 debug stbus dual fdma l2 cache delta mu dual usb esata/pci-e sd-mmc/sdio pcm reader pcm players dacs vtgs analog video hdmi smartcard stfe slc nand flash serial flash ci-plus cards ddr3 key scan stbe transport streams parallel/serial in/out low power standby controller hdcp ethernet ddr3 lmi www.st.com
introduction stih206 2/4 docid024749 rev 1 1 introduction the stih206 offers current users of st?s growing family of advanced decoding ics enhancements in performance and features, enabling operators to offer consumers new multimedia-rich services and viewing experien ces, including new 3dtv features. faster ddr3 memory is also supported, and the applic ations cpu benefits from an l2 cache. the stih206 keeps pace with the latest advanced security requirements of the main ca vendors, and an integrated standby controller enables the stih206 to target stringent low power regulations. features benefits st40 applications cpu, with 32 kbyte i and 32 kbyte d l1 caches and 256 kbyte l2 cache. high performance processing for applications and middleware. integrated low power standby controller within its own power island. secure hibernation to, and fast resume from, very low power passive standby mode, targeting stb standby power < 0.5 w. latest generation of st's delta video decoder with an st231-based multi-codec capable controller, coupled with a high quality video display pipeline (hqvdp). decoding of advanced high definition standards (mpeg2, h264, vc-1, avs) plus the performance and flexibility for web-based content decoding such as flash ? , divx?, mjpeg and real ? , without impacting applications cpu performance. dual usb 2.0 hosts, esata, ethernet mac with mii/rmii/tmii interfaces, pci-e, sd-mmc/sdio interface. extensive high speed connectivity for the widest range of stb peripherals, such as flash drives, external hdds, ethernet, home network controllers (such as moca ? , wi-fi), docsis ? modem and memory cards. nocs3.0, nsk2.0 and dvb-csa3 ready. fully compliant with the latest advanced security requirements of ca vendors.
docid024749 rev 1 3/4 stih206 revision history 4 2 revision history table 1. document revision history date revision changes 06-jun-2013 1 initial release.
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